1. Field of the Invention
The present invention relates to a chip package, and more particularly to an embedded chip package with improved heat dissipation performance.
2. Description of the Prior Art
With the rapid development of electronic technology, the number of I/O pads in microcontrollers is drastically increasing, and the power that each silicon chip consumes has also increased. In the future, microcontrollers may have more pins. For chip packages, electrical performance and dissipation control are two major challenges. In the aspect of electrical performance, chip packages have to maintain integrity of signals and operating frequency of semiconductor devices. In the aspect of dissipation control, chip packages also help dissipate heat generated by the silicon chip.
In addition to electrical performance and dissipation control, the small size of the microcontroller also demands smaller chip package size and denser I/O pad arrangements. In the future, a chip package may comprise several dies and opto-electronic elements, and minimizing the space between elements, maximizing the interconnectivity of elements, controlling signal frequency precisely, and matching impedance will be great issues for chip package designers. In conclusion, the prior art package technology, such as FCPGA, will not satisfy new requirements.
To solve the problems mentioned above, Intel Corp. has developed a Bumpless Build-Up Layer (BBUL) technology that embeds a die into a specialized, pc-board-like package, getting rid of solder bumps and connecting copper wires on the substrate directly.
FIG. 1 to FIG. 7 are schematic diagrams of conventional BBUL package technology. As shown in FIG. 1, a substrate 10 comprising a top surface 10a and a bottom surface 10b is provided. Please refer to FIG. 2. FIG. 2 depicts a through hole 12 formed by penetrating both the top surface 10a and the bottom surface 10b of the substrate 10.
Then, as shown in FIG. 3, a layer of tape 14 comprising an adhesive layer 13 is stuck to the bottom surface 10b of the substrate 10. The adhesive layer 13 causes the tape 14 to stick to the bottom surface 10b of the substrate 10. The tape 14 and the through hole 12 form a recessed cavity 15.
As shown in FIG. 4, an active surface 20a of a die 20 put facedown into the recessed cavity 15. A plurality of bonding pads 22 is positioned on the active surface 20a; a bottom surface 20b of the die 20 is toward up and a bottom surface 20b is coplanar with the top surface 10a of the substrate 10. The die 20 adheres to the tape 14 through the adhesive layer 13.
Then, as shown in FIG. 5, the gap between the substrate 10 and the die 20 is filled by an underfill 30 to fix the die 20 in the substrate 10. Next, as shown in FIG. 6, the tape 14 is torn off, exposing the active surface 20a of the die 20.
Finally, as shown in FIG. 7, the bottom surface 10b of the substrate 10 and the active surface 20a of the die 20 are routed, forming an interconnect layer 40 comprising a dielectric layer 42, a dielectric layer 44, a dielectric layer 46, wires in the dielectric layers, a solder resist layer 48 and bumps 49.
In the prior art BBUL technology, defects often occur during the process of routing wires on the surface layers. For example, after tearing off the tape 14, adhesive residue may be left on the bonding pads 22 positioned on the active surface 20a of the die 20. This problem decreases product quality, and increases the product cost so that the BBUL package may cost much more than the conventional package method.
Furthermore, because of the difference in the coefficients of thermal expansion of the die 20, the underfill 30 and the substrate 10, cracks may occur during the routing process. Moreover, the heat dissipation performance also needs to be improved in the conventional BBUL package, so there are still a lot of problems to be solved in the conventional BBUL package.